Can I have conditional constants in VHDL? -

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i have entity has generic integer parameter fs_in_khz can 5, 10 or 2:

entity test_control_source     generic(         -- should 5, 10 or 20         fs_in_khz : integer := 20     );

it nice if take advantage of vhdl's features , restrict type values, perhaps using like:

type control_source_freq (f5_khz, f10_khz, f20_khz); ... entity test_control_source generic(     -- should 5, 10 or 20     fs_in_khz : control_source_freq := f20_khz );

however, later on in architecture of entity, have

architecture source_behaviour of test_control_source     constant cs_period : integer := 5000 * clock_rate / fs_in_khz; begin     ...

i prefer having parameter computed outside of processes use it, rather repeating computation everywhere it's needed. can restrict allowed values of fs_in_khz generic parameter and keep constant cs_period factored out of processes it's used?

create enumerated type in package, suggest

also create function called calculate_period takes in clock_rate , fs type , returns appropriate integer.

alternatively, add assert statements component using generic , verify of correct values. test synthesis tool see happens if asserts trigger though - often, if use severity failure it'll give warning!


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